Integrated circuits are chemically and physically integrated into a substrate, such as a silicon wafer, by patterning regions in the substrate, and by patterning layers on the substrate. These regions and layers can be conductive, for conductor and resistor fabrication. They can also be of different conductivity types, which is essential for transistor and diode fabrication.
Deposited conductors are an integral part of every integrated circuit, and provide the role of surface wiring for conducting current. Specifically, the deposited conductors are used to wire together the various components that are formed in the surface of the wafer. Electronic devices formed within the wafer have active areas which must be contacted with conductive runners, such as metal. Typically, a layer of insulating material is applied atop the wafer and selectively masked to provide contact opening patterns. The layer is subsequently etched to provide contact openings from the upper surface of the insulating layer down into the wafer to provide electrical contact with selected active areas.
Certain metals and alloys do not provide the most desired coverage within the contact openings when applied to the surface of a wafer. This is illustrated with reference to FIG. 1. There illustrated is a diagrammatic section view of a wafer substrate 10 having a pair of contact openings 12, 14 formed therein. A metal layer 16 has been applied to substrate 10. As illustrated, layer 16 provides poor, incomplete coverage within openings 12 and 14. An example of a metal which typically provides such poor coverage is aluminum, or alloys of aluminum with silicon and/or copper.
One metal which does provide good coverage within contact vias is tungsten. FIG. 2 illustrates a layer of tungsten 18 having been applied atop wafer 10. As illustrated, complete coverage occurs within contact openings 12 and 14. Tungsten is not, however, as conductive as aluminum. Accordingly, tungsten contacts are typically etched or polished back to provide a flush upper surface layer with the upper portion of the substrate, such as is illustrated by FIG. 3. A layer of aluminum would thereafter be applied atop wafer 10 (not shown), and selectively etched to provide the desired interconnecting runs.
FIG. 4 illustrates one problem with certain etch backs of tungsten, namely an etch which is selective to the surrounding wafer but over etches within the contacts. This can provide for poor coverage within the contacts of the aluminum or aluminum alloy layer which would be applied subsequently.
A need remains for improved methods of etching back tungsten layers on semiconductor wafers.